By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® describes the complex ideas and methods used for ASIC chip synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the total ASIC layout movement method distinctive for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time program of Synopsys instruments used to strive against a variety of difficulties obvious at VDSM geometries. Readers might be uncovered to a good layout technique for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, and static timing research. At every one step, difficulties with regards to each one section of the layout circulation are pointed out, with options and work-arounds defined intimately. moreover, the most important matters with regards to structure, which include clock tree synthesis and back-end integration (links to structure) also are mentioned at size. moreover, the booklet includes in-depth discussions at the fundamentals of Synopsys expertise libraries and HDL coding kinds, distinct in the direction of optimum synthesis suggestions.
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® is meant for a person who's enthusiastic about the ASIC layout technique, ranging from RTL synthesis to ultimate tape-out. objective audiences for this publication are training ASIC layout engineers and graduate scholars project complex classes in ASIC chip layout and DFT ideas.
From the Foreword:
`This e-book, written by means of Himanshu Bhatnagar, presents a accomplished assessment of the ASIC layout movement specific for VDSM applied sciences utilizing the Synopsis suite of instruments. It emphasizes the sensible matters confronted through the semiconductor layout engineer by way of synthesis and the mixing of front-end and back-end instruments. conventional layout methodologies are challenged and special ideas are provided to assist outline the following iteration of ASIC layout flows. the writer offers a variety of useful examples derived from real-world events that might turn out worthy to practising ASIC layout engineers in addition to to scholars of complicated VLSI classes in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant structures, Inc., (Formerly, Rockwell Semiconductor Systems), Newport seashore, CA, USA.
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Extra resources for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®
The estimated delays are back annotated to PrimeTime for analysis, ASIC DESIGNMETHODOLOGY 13 and only when the timing is considered satisfactory, the remaining process is allowed to proceed. Detailed routing is the final step that is performed by the layout tool. After detailed route is complete, the real timing delays of the chip are extracted, and plugged into PrimeTime for analysis . These steps are iterative and depend on the timing margins of the design. If the design fails timing requirements, post-layout optimization is performed on the design before undergoing another iteration of layout.
An example design was used to guide the reader from start to finish. At each stage, brief explanation and relevant scripts were provided. The chapter started with basics of setting up the Synopsys environment and technical specification of the example design. Further sections were divided into pre-layout, floorplanning and routing, and finally the post-layout steps. The pre-layout steps included initial synthesis and scan insertion of the design, along with static timing analysis, and SDF generation for dynamic simulation.
The concept of formal verification was introduced to overcome these issues, which are discussed in the next section. Let us assume that the tap_controller design is passing all the functional vectors with no setup or hold-time violations, using the pre-layout SDF generated previously . 2 Formal Verification Synopsys recently introduced a tool that is capable of performing formal verification, called Formality. Formality uses mathematical algorithms in order to check the logic equivalency of a design.