By Himanshu Bhatnagar
Complicated ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment version describes the complicated strategies and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. additionally, the whole ASIC layout circulate technique detailed for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time software of Synopsys instruments, used to wrestle quite a few difficulties noticeable at VDSM geometries. Readers could be uncovered to a good layout technique for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, actual synthesis, and static timing research. At every one step, difficulties on the topic of every one part of the layout circulation are pointed out, with strategies and work-around defined intimately. additionally, an important matters concerning format, including clock tree synthesis and back-end integration (links to format) also are mentioned at size. moreover, the e-book includes in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding types, unique in the direction of optimum synthesis resolution. aim audiences for this publication are practising ASIC layout engineers and masters point scholars venture complicated VLSI classes on ASIC chip layout and DFT concepts.
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Extra resources for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
1 Pre-Layout Steps The following sub-sections illustrate the steps involved during the pre-layout phase. This includes one-pass logic synthesis with scan insertion, static timing analysis, SDF generation to perform functional gate-level simulation, and finally formal verification between the source RTL and synthesized netlist. db technology library. In order to maximize the setup-time, you may constrain the design by defining clock uncertainty for the setup-time. In general, a 10% over-constrain is usually sufficient, in order to minimize the synthesis-layout iterations.
Therefore, this step will not be explained in subsequent chapters. ASIC DESIGN METHODOLOGY 13 Many designers regard engineering change order (ECO) as the change required in the netlist at the very last stage of the ASIC design flow. For instance, ECO is performed when there is a hardware bug encountered in the design at the very last stage (say, after tape-out), and it is necessary to perform a metal mask change by re-routing a small portion of the design. As a result ECO is performed on a small portion of the chip to prevent disturbing the placement and routing of the rest of the chip, thereby preserving the rest of the chip’s timing.
The JTAG controller and surrounding logic may also be generated directly by DC. 4 Formal Verification The concept of formal verification is fairly new to the ASIC design community. Formal verification techniques perform validation of a design using mathematical methods without the need for technological considerations, such as timing and physical effects. They check for logical functions of a design by comparing it against the reference design. ASIC DESIGN METHODOLOGY 9 A number of EDA tool vendors have developed the formal verification tools.